Save the Date for IWLPC 2016!
October 18 - 20, 2016
San Jose, California, USA

SMTA and Chip Scale Review are pleased to announce the 13th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging.






Submit an abstract for IWLPC 2016!


Deadline for submission of abstracts for the 2016 program has been extended to May 6th, 2016.
Click here to submit an abstract!






New Manufacturing Challenges Sub-track added!


This year, we will have a separate sub-track to focus on manufacturing challenges to high volume production, and strategies to address them. This includes challenges such as quality and yield, equipment throughput, processing and equipment control, cycle time, materials, automation and logistics. Abstracts can cover WLP, MEMS & 3D manufacturing.

Topics covered:
  • Quality and yield
  • Equipment throughput
  • Processing and equipment control (SPC, APC, FDC)
  • Factory output & cycle time
  • Materials
  • Automation
  • Logistics





  • Lang and Tummala to Keynote IWLPC


    The SMTA and Chip Scale Review magazine are pleased to announce the Keynote Presenters for the 13th Annual International Wafer-Level Packaging Conference.

    October 18, 2016

    Advanced Technology Platforms for Next Generation of Smart Systems

    Klaus-Dieter Lang, Ph.D., Fraunhofer IZM

    Klaus-Dieter Lang

    The trend to establish smart electronic systems in an increasing number of application fields (e.g. Internet of Things) is enormous. But because of huge product variation main precondition to manufacture such systems are complex design tools, standardized leading edge processes and system oriented test procedures. The allocation of innovative technology platforms (e.g. advanced assembly and packaging) and extended test principles (e.g. technology and functionality) are needed to achieve high yields and reasonable costs. Presentation topics include application conditions, integration technologies and reliability aspects for smart electronic systems. Examples from wearables, communication and production illustrate the advantage of their use.

    Prof. Lang studied Electrical Engineering and received his M.S. Equivalent Diploma (Metallization Layers on GaAs). In 1985, he received his Ph.D. and 1989 he got his Doctor of Technical Science. In 1993, he became Section Manager for Chip Interconnections at Fraunhofer IZM and from 2003 he headed the Department "Photonic and Power System Assembly". Since 2011, he is Director of the Fraunhofer IZM and responsible for the chair "Nano Interconnect Technologies" at Technical University Berlin.



    October 19, 2016

    New Era of Automotive Electronics: The Ultimate Electronics Systems Opportunity

    Rao R. Tummala, Ph.D., Georgia Institute of Technology

    Rao Tummala

    The new trends in automotive electronics such as autonomous driving, in-car smartphone-like infotainment, privacy and security, and all-electric cars, require an entirely different vision than is pursued today. Georgia Tech sees unprecedented challenges and opportunities to address these needs and proposes a systematic approach to system scaling, innovative device and package architectures and heterogeneous integration for the new era in electronics hardware with particular focus in electrical, mechanical and thermal designs and new digital, RF, radar, lidar camera, millimeter wave, high power and high temperature technologies.

    Prof. Rao Tummala is a Distinguished and Endowed Professor Chair at Georgia Tech. He is well known as an industrial technologist, technology pioneer, and educator. He is the father of LTCC and System-on-Package Technologies.

    Find out more!






    IWLPC Technical Chair Announced

    Chris Scanlan, Deca Technologies

    Chris Scanlan joined Deca Technologies, Inc. in November 2009. A 17-year veteran of the semiconductor industry, his focus is interconnect technology development and product line management. Mr. Scanlan began his career at Motorola, where he developed a highly automated process for the manufacture of IGBT hybrid power modules, and later managed the development and deployment of flip-chip technology within Motorola’s Advanced Interconnect Systems Laboratory. Amkor Technology, Inc. tapped his talent for a decade. There he held Vice President positions in the areas of research and development, product management, and applications engineering. Mr. Scanlan has more than 25 US patents relating to semiconductor assembly technologies.

    Find out more!






    Best Presentation & Papers Awards Announced


    General Chair, IWLPC 2015 Steven Xu, Ph.D. Qualcomm announces the Best of Conference, Best Presentation & Best Papers in WLP, 3D, MEMS program tracks as chosen by the technical committee from the respective technical tracks based on technical merit, relevance, originality, knowledge of subject, quality of material and quality of presentation.

  • Best of Conference Paper: Lutz Hofman of Fraunhofer ENAS
    "3D Wafer-Level Packaging by using Cu-Through Silicon Vias for Thin MEMS Accelerometer Packages"

  • Best of Conference Presentation: Chet Palesko of Savansys Solutions
    "Technology and Cost Comparison of Electronic Packaging Methods"

  • Best of 3D track paper: Tom Strothmann of Kulicke & Soffa
    "Methods for Assembly of TSV Products"

  • Best of WLP track paper: Thomas Uhrmann EV Group / Jose Campos NANIUM
    "Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP"

  • Best of MEMS track paper: Lutz Hofman of Fraunhofer ENAS
    "3D Wafer-Level Packaging by using Cu-Through Silicon Vias for Thin MEMS Accelerometer Packages"






    IWLPC General Chair Announced


    Curtis Zwenger SMTA and Chip Scale Review magazine are pleased to announce Curtis Zwenger, Amkor Technology’s Senior Director, Advanced Package Technology and Integration, as the new General Chair for the 13th Annual International Wafer-Level Packaging Conference held October 18-20, 2016 in San Jose, CA.

    Curtis was selected by SMTA/Chip Scale Review Magazine to serve as General Chair. As general chair, he will work closely with the Technical Chair, Advisory Committee, SMTA Education Manager and Chip Scale Review to manage and direct the activities of the entire committee and ensure critical tasks remain on schedule. Under his leadership, they will build a strong technical conference that includes two days of three tracks with technical paper presentations covering Wafer Level Packaging, 3-D (Stacked) Packaging, and MEMS Packaging. He previously served as the WLP Track Chair where he helped identify and build high quality speakers and topics in the WLP track.

    Curtis holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix. He has over 20 years of experience in the semiconductor industry and is currently responsible for the development and commercialization of Amkor’s Advanced Wafer-Level Fan-Out and Glass Substrate product lines. He joined Amkor Technology in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and MEMS packaging technologies. Prior to joining Amkor, he worked for Motorola. He has published several papers and holds 12 patents related to semiconductor package engineering.

    Interconnecting Wafer-Level packaging, 3D, and MEMS, the International Wafer-Level Packaging Conference (IWLPC) has been at the forefront of packaging technology evolution; it is one of the premier packaging conferences. Attendees from over 16 countries gather in the heart of Silicon Valley to attend IWLPC to enrich themselves on the latest technology and business trends. Going into its 13th year the IWLPC is co-produced by Chip Scale Review, the leading international magazine addressing the semiconductor packaging industry and SMTA, the distinguished global association in electronic assembly and manufacturing.

    If you would like to present at this conference, please submit a 200-300 word abstract by April 15, 2016. Please include a title, author name, and contact information with your abstract. Technical papers and presentations are required and will be due September 4, 2016.

    For more information, please contact Jenny Ng at 952-920-7682 or jenny@smta.org.





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    Organized by SMTA and ChipScale Review



    Supported by:
    MEMS Journal MEPTEC Roger Grace Associates