Save the Date for IWLPC 2016!
October 18 - 20, 2016
San Jose, California, USA

SMTA and Chip Scale Review are pleased to announce the 13th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.






Program Finalized and Registration Now Open!

Interconnecting Wafer-Level packaging, 3D, and Manufacturing, the International Wafer-Level Packaging Conference (IWLPC) has been at the forefront of packaging technology evolution; it is one of the premier packaging conferences. Attendees from over 16 countries gather in the heart of Silicon Valley to attend IWLPC to enrich themselves on the latest technology and business trends. Going into its 13th year the IWLPC is co-produced by Chip Scale Review, the leading international magazine addressing the semiconductor packaging industry and SMTA, the distinguished global association in electronic assembly and manufacturing.

View the Conference brochure (PDF) for details.



New Manufacturing Challenges Sub-track added!


This year, we will have a separate sub-track to focus on manufacturing challenges to high volume production, and strategies to address them. This includes challenges such as quality and yield, equipment throughput, processing and equipment control, cycle time, materials, automation and logistics. Abstracts can cover WLP, MEMS & 3D manufacturing.

Topics covered:
  • Quality and yield
  • Equipment throughput
  • Processing and equipment control (SPC, APC, FDC)
  • Factory output & cycle time
  • Materials
  • Automation
  • Logistics





  • Lang and Tummala to Keynote IWLPC


    The SMTA and Chip Scale Review magazine are pleased to announce the Keynote Presenters for the 13th Annual International Wafer-Level Packaging Conference.

    October 18, 2016

    Advanced Technology Platforms for Next Generation of Smart Systems

    Klaus-Dieter Lang, Ph.D., Fraunhofer IZM

    Klaus-Dieter Lang

    Klaus-Dieter Lang, Ph.D., Fraunhofer IZM is scheduled to give the keynote presentation on the first day of the conference on “Advanced Technology Platforms for Next Generation of Smart Systems.” The trend to establish smart electronic systems in an increasing number of application fields (e.g., Internet of Things) is enormous. But because of huge product variation, the main precondition to manufacture such systems is complex design tools, standardized leading edge processes, and system oriented test procedures. The allocation of innovative technology platforms (e.g., advanced assembly and packaging) and extended test principles (e.g., technology and functionality) are needed to achieve high yields and reasonable costs. Presentation topics include application conditions, integration technologies and reliability aspects for smart electronic systems. Examples from wearables, communication and production illustrate the advantage of their use.

    Prof. Lang studied Electrical Engineering and received his M.S. Equivalent Diploma (Metallization Layers on GaAs). In 1985, he received his Ph.D. and in 1989 he received his Doctor of Technical Science. In 1993, he became Section Manager for Chip Interconnections at Fraunhofer IZM and from 2003 he headed the Department "Photonic and Power System Assembly.” Since 2011, he has been the Director of the Fraunhofer IZM and responsible for the chair "Nano Interconnect Technologies" at the Technical University Berlin.



    October 19, 2016

    Promise and Future of Embedding and Fan-Out Technologies

    Rao R. Tummala, Ph.D., Georgia Institute of Technology

    Rao Tummala

    Rao R. Tummala, Georgia Institute of Technology, Ph.D., will deliver the keynote on the second day, entitled "Promise and Future of Embedding and Fan-Out Technologies.” All packaging technologies can be classified into two types. Wafer-level packaging (WLP) is one approach with ICs built directly into packages in the wafer fab by simply redistributing the BEOL I/Os and placing bumps. This is the best package electrically, but it is limited to small ICs and to small packages—typically below 5mm. As such, it is limited in external I/Os to connect to the board, typically at 400 microns and above in pitch.

    To eliminate the I/O limitation issue noted above, fan-out technology was initially developed in the 1980s and more recently further developed into production by Infineon. But this technology is not a wafer-level packaging, as described above; it is not a continuum of transistors to bumps. It did, however, address the I/O limitation. It is primarily an embedded packaging technology called, eWLP, that allowed fan-out of I/Os, in contrast to WLP, but also enabled embedding to reduce package thickness. This presentation will describe the promise and future of embedding and fan-out technologies.

    Prof. Rao Tummala is a Distinguished and Endowed Professor Chair at Georgia Tech. He is well known as an industrial technologist, technology pioneer, and educator. He is the father of LTCC and System-on-Package Technologies.

    Find out more!






    IWLPC Technical Chair Announced

    Chris Scanlan, Deca Technologies

    Chris Scanlan joined Deca Technologies, Inc. in November 2009. A 17-year veteran of the semiconductor industry, his focus is interconnect technology development and product line management. Mr. Scanlan began his career at Motorola, where he developed a highly automated process for the manufacture of IGBT hybrid power modules, and later managed the development and deployment of flip-chip technology within Motorola’s Advanced Interconnect Systems Laboratory. Amkor Technology, Inc. tapped his talent for a decade. There he held Vice President positions in the areas of research and development, product management, and applications engineering. Mr. Scanlan has more than 25 US patents relating to semiconductor assembly technologies.

    Find out more!






    Best Presentation & Papers Awards Announced


    General Chair, IWLPC 2015 Steven Xu, Ph.D. Qualcomm announces the Best of Conference, Best Presentation & Best Papers in WLP, 3D, MEMS program tracks as chosen by the technical committee from the respective technical tracks based on technical merit, relevance, originality, knowledge of subject, quality of material and quality of presentation.

  • Best of Conference Paper: Lutz Hofman of Fraunhofer ENAS
    "3D Wafer-Level Packaging by using Cu-Through Silicon Vias for Thin MEMS Accelerometer Packages"

  • Best of Conference Presentation: Chet Palesko of Savansys Solutions
    "Technology and Cost Comparison of Electronic Packaging Methods"

  • Best of 3D track paper: Tom Strothmann of Kulicke & Soffa
    "Methods for Assembly of TSV Products"

  • Best of WLP track paper: Thomas Uhrmann EV Group / Jose Campos NANIUM
    "Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP"

  • Best of MEMS track paper: Lutz Hofman of Fraunhofer ENAS
    "3D Wafer-Level Packaging by using Cu-Through Silicon Vias for Thin MEMS Accelerometer Packages"






    IWLPC General Chair Announced


    Curtis Zwenger SMTA and Chip Scale Review magazine are pleased to announce Curtis Zwenger, Amkor Technology’s Senior Director, Advanced Package Technology and Integration, as the new General Chair for the 13th Annual International Wafer-Level Packaging Conference held October 18-20, 2016 in San Jose, CA.

    Curtis was selected by SMTA/Chip Scale Review Magazine to serve as General Chair. As general chair, he will work closely with the Technical Chair, Advisory Committee, SMTA Education Manager and Chip Scale Review to manage and direct the activities of the entire committee and ensure critical tasks remain on schedule. Under his leadership, they will build a strong technical conference that includes two days of three tracks with technical paper presentations covering Wafer Level Packaging, 3-D (Stacked) Packaging, and MEMS Packaging. He previously served as the WLP Track Chair where he helped identify and build high quality speakers and topics in the WLP track.

    Curtis holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix. He has over 20 years of experience in the semiconductor industry and is currently responsible for the development and commercialization of Amkor’s Advanced Wafer-Level Fan-Out and Glass Substrate product lines. He joined Amkor Technology in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and MEMS packaging technologies. Prior to joining Amkor, he worked for Motorola. He has published several papers and holds 12 patents related to semiconductor package engineering.

    For more information, please contact Jenny Ng at 952-920-7682 or jenny@smta.org.





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    Organized by SMTA and ChipScale Review



    Supported by:
    MEMS Journal MEPTEC MCA Public Relations Roger Grace Associates