Driving an Interconnected World
October 23 - 25, 2018
DoubleTree by Hilton San Jose
San Jose, California, USA

IWLPC 2018

October 23 - 25, 2018
DoubleTree by Hilton San Jose
San Jose, California, USA

SMTA and Chip Scale Review are pleased to announce the 15th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.







Program Finalized and Registration Now Open!

Interconnecting Wafer-Level Packaging, 3D Packaging, Advanced Manufacturing and Test, the International Wafer-Level Packaging Conference (IWLPC) is at the forefront of the packaging technology evolution. The Wafer-Level Packaging (WLP) track features sessions on package reliability, integration technology, wafer-level fan-out process and metrology, and panel-level fan-out packaging. The 3D Packaging track features sessions on processing technologies, advanced technologies, processing & materials, and wafer bonding applications. The Advanced Manufacturing track features sessions on inspection & test, new methods & materials, process and technology.

Get details on the technical program!







Keynote Speakers Announced


Douglas C.H. Yu, Ph.D

Growth of WLSI and Wafer Foundry with Moore's Law and More-than-Moore, and Vice Versa

Douglas C.H. Yu, Ph.D.

Vice President, Research & Development
Taiwan Semiconductor Manufacturing Company (TSMC)


Walden Rhines, Ph.D.

Monolithic versus Heterogeneous Packaging: Where Does the Future Lie?

Walden Rhines, Ph.D.

President and Chief Executive Officer
Mentor, a Siemens business


Veer Dhandapani, Ph.D.

Interconnected World and the Automotive Paradigm

Veer Dhandapani, Ph.D.

Head of Automotive Packaging
NXP Semiconductors

Get details!





Photos from IWLPC 2017





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Organized by: SMTA and ChipScale Review



Supported by:
MEPTEC Panel Level Packaging Consortium