Technical Conference Sessions: October 24-25, 2017
Workshops: October 26, 2017The IWLPC workshops are application-oriented and structured to combine field experience with scientific research to solve everyday problems.
Fan Out Packaging – Technology Overview and EvolutionJohn Hunt, ASE (US) Inc.
8:30am–12:00pm | San Martin
Mobile electronics has driven the need for ever increasing density and performance in electronics packaging. This has only accelerated with the advent of advanced smart phones and the burgeoning Internet of Things. This evolution has led to a need for higher levels of component density and functionality than has been traditionally available using standard packaging, resulting in a wide variety of new packaging options.
We will review how the integration of wafer level processing technologies, substrate evolution and Flip Chip packaging structures have come together into what is being called Fan Out Packaging. These packages are for both low density and high density, Mobile and server applications. They have higher levels of integration and sophistication than has ever been possible in the past. These options include Wafer Level Fan Out, Panel Level Fan Out, and Chip Last Fan Out packaging. All of these can combine low cost materials and varied process flows to create both simple devices, and more complex System in Package and Package on Package applications. This course will provide an overview of the drivers, technology, advantages and disadvantages of various structural and processing options, as well as a view of potential future trends for Fan Out Packaging.
1. Evolution to Fan Out
b. Fan Out
2. Drivers for Fan Out
a. Historical Drivers
b. Advanced Drivers
3. Definition of “Fan Out”
4. Advantages of Fan Out
5. Fan Out Market
b. Low Density vs High Density
6. Brief History of Fanout
a. Early Variations
7. 2D Fan Out Structures
a. Low Density 2D Fan Out
b. High Density 2D Fan Out
8. Fan Out System in Package (SiP)
a. Passive Components in Fan Out
b. 3D Interconnectivity Structures
9. 3D Fan Out Structures
a. Low Density 3D Fan Out
b. High Density 3D Fan Out
10. Discussion of Processes & Structures
a. Potential Processing Issues
b. Specific Structures & Processes
c. Comparison of Fan Out Technologies
11. Reliability Considerations
a. Structural Reliability Variations
12. Panel Fan Out
Package on Package, Design, Process and QualityFernando Roa, Ph.D., Amkor Technology
8:30am–12:00pm | San Carlos
This course will provide an introduction to design, packaging and reliability fundamentals required in the definition, process development and production of package on package applications. As such, we'll delve into critical design rules to observe during the layout of the substrates required for such packaging as well as best known methods for assembly including rules of thumb for selection of materials. The course will also include typical process flows used based on final EMS implementation of these PoPs and quality metrics to use.
• What is a PoP and where is used
• PoP Components
• Types of PoPs and characteristics for each:
i. Bare die,
iii. Molded with TMV
iv. Package considerations for
• Package constraints and considerations
iii. electrical constraints
iv. Total thickness
• Substrate design rules for Bottom PoP
• Top package selection
• Material selection:
• Process flows for assembly
• Typical assembly equipment
• EOL: SMT vs pre-stacking
4. Quality & reliability
• Typical characterization and quality metrics for PoPs
5. Costing & supply chain
Who Should Attend?
Design, product and process engineers, managers, procurement organizations from OEM and IDM organizations operating the baseband, AP and advanced packaging of components; also, CM and EMS representatives which are receiving PoPs for integration on boards.
Fan-Out Wafer-Level Packaging and 3D PackagingJohn Lau, Ph.D., ASM Pacific Technology
1:30pm-5:00pm | San Carlos
Recent advances in, e.g., fan-out wafer/panel level packaging (TSMC’s InFO-WLP and Fraunhofer IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (Xilinx/TSMC’s CoWoS and TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, 3D MEMS/IC integration, and Cu-Cu hybrid bonding will be discussed in this presentation. Emphasis is placed on various FOWLP assembly methods such as chip-first with die-up, chip-first with die-down, and chip-last (RDL-first). Since RDLs (redistribution layers) play an integral part of FOWLP, various RDL fabrication methods such as Cu damascene, polymer, and PCB (printed circuit board) will be discussed. A few notes and recommendations on wafer vs. panel, dielectric materials, and molding materials will be provided. Also, TSV-less interposers such as those given by Xilinx/SPIL, Amkor, SPIL/Xilinx, ASE, MediaTek, Intel, ITRI, Shinko, Cisco/eSilicon, Samsung, and Sony will also be discussed. Furthermore, new trends in semiconductor packaging will be presented.
B. Fan-Out Wafer/Panel-Level Packaging
(1) Patents Impacting the Semiconductor Packaging
(2) Fan-out Wafer/Panel-Level Packaging Formations: Chip-first (die-down), Chip-first (die-up), Chip-last (RDL-first)
(3) RDL Fabrications: Polymer method, PCB/LDI method, Cu damascene method
(4) TSMC InFO-WLP
(5) TSMC InFO-PoP vs. Samsung ePoP
(6) Wafer vs. Panel Carriers
(7) Notes on Dielectric and Epoxy Mold Compound
(8) Semiconductor and Packaging for IoTs (SiP)
(9) Wafer/Panel-Level System-in-Package (WLSiP and PLSiP)
(10) Package-Free LED (Embedded LED CSP)
(11) SMT assembly of fan-out package
C. 3D IC Integration with TSVs
(1) Memory Chip Stacking – Samsung’s DDR4
(2) Hybrid Memory Cube (HMC) – Micron/Intel’s Knights Landing
(3) High Bandwidth Memory (HBM) – Hynix/AMD’s and Samsung/Nvidia’s GPU
(4) Chip stacking by TCNCF
(5) Samsung’s Widcon
(6) 3D IC/CIS Integration
(7) 3D IC/MEMS Integration
(8) Embedded 3D Hybrid Integration
D. 2.5D IC Integration and TSV-Less Interposers
(1) TSMC/Xilinx’s CoWoS
(2) Xilinx/SPIL’s TSV-less SLIT
(3) SPIL/Xilinx’s TSV-less NTI
(4) Amkor’s TSV-less SLIM
(5) ASE’s TSV-less FOCoS
(6) MediaTek’s TSV-less RDLs by FOWLP
(7) Intel’s TSV-less EMIB
(8) Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM
(9) ITRI’s TSV-less TSH
(10) Shinko’s TSV-less i-THOP
(11) Cisco/eSilicon’s TSV-less Organic Interposer
(12) Samsung’s TSV-less Organic Interposer
(13) Sony’s TSV-less CIS (Cu-Cu Hybrid Bonding
E. Semiconductor Packaging and Assembly New Trends
F. Summary and Q&A
Who Should Attend
If you are involved with any aspect of the electronics assemblies, you should attend this course. All the materials are based on the papers and books published in the past 3 years and each participant will receive more than 200 pages of the lecture notes.
Dr. John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was an ITRI Fellow of Industrial Technology Research Institute (Taiwan) for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at Hewlett-Packard/Agilent in California, US for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 441 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.
Future of Packaging: Embedded and Non-embedded and Fan-outRao R. Tummala, Ph.D., Georgia Institute of Technology
1:30pm-5:00pm | San Martin
Semiconductor and systems landscape is changing dramatically. ICs, on one hand, for the most part, are becoming commodities, providing much lower profit margins than ever before, leading to industry consolidation to less than ten manufacturing companies within the next decade, worldwide. In addition, the cost and complexity of transistor scaling is growing exponentially. There is no longer a cost reduction as the next node is introduced with higher transistor density. In addition, IC performance is being greatly impacted by interconnect delay and leakage. The driving engines for electronic systems, on the other hand, are also changing dramatically to smart, wearable, wireless healthcare, wireless networks and new era of self-driving and electric cars, requiring an entirely different vision and strategy than transistor scaling alone that has been and continues to be practiced during the last 60 years. These systems are small to ultra-small systems and yet must perform dozens of functions that include high-speed digital, high-efficiency power, 5G and millimeter wave, MEMS and sensors.
The new era of automotive electronics, in addition, requires a variety of sensing technologies for self-driving cars such as camera, LiDAR and radar, and ultra-high power for electric cars. All these emerging or next generation computing, communications, consumer and automotive systems pose device, packaging and integration barriers like never before. They require a new role for packaging. Unlike in the past, future packaging must add value in making better devices and better systems by addressing the device and system barriers by enabling better and cheaper devices and highly-integrated and ultra-miniaturized systems. The advances need to be more than Moore's (MTM) Law with on-chip transistor integration in 2D and 2.5D MCM, 3D stacked ICs with TSV and SIP. They require a new paradigms in systems packaging, referred to as “System Moore’s” Law (SM) for complete systems by a new and innovative 3D system concept. Such a new system package architecture concept goes beyond SIP, 2.5D and 3D with TSV. The course will review the current approach to devices, device packaging and system packaging. These include traditional single- and multi-chip packaging as well as the recent focus in embedded and fan-out packaging. This course sets the stage for new era in value-add packaging and new strategic technologies, manufacturing infrastructures and applications.
Who Should Attend?
Senior marketing and R&D executives as well as senior managers who are dealing with strategic issues facing the electronics industry should attend.
Prof. Rao Tummala is a Distinguished and Endowed Chair Professor at Georgia Tech USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the industry’s first plasma display and the first and next three generations of 100 chip multi-chip packaging. He is the father of LTCC and System-on-Package technologies. As an educator, Prof. Tummala was instrumental in setting up the largest Academic Center in Electronic Systems at Georgia Tech involving more than 100 PhD and MS students, 25 faculty from ECE, ME, MSE and CHE, and 70 companies from the U.S., Europe and Asia, all working together with an integrated approach to research, education and industry collaborations. He has published 900 technical papers and invented over 100 patents, wrote the first textbook in packaging, Microelectronics Packaging Handbook; wrote the 1st undergrad textbook, Fundamentals of Microsystem Packaging; and the 1st SOP book, Introduction to System-on-Package.